1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for fabricating a semiconductor device which can improve electrical properties of the semiconductor device, by preventing short from occurring between an interconnection line and a metal electrode.
2. Description of the Background Art
Recently, integration of a semiconductor device has been remarkably improved. As a result, there is a strong demand for a method for easily fabricating a transistor and planarizing an interlayer insulating film to enhance the integration of the semiconductor device.
So as to maximize a planarization property, a method for improving the planarization property according to an etching process has been mostly performed on borophosphosilicate glass (BPSG) film used for planarization of the interlayer insulating film, after performing a flow (or reflow) process at a high temperature.
When performed at temperatures over 820xc2x0 C., the high temperature flow process can improve the planarization property of the BPSG film. However, impurities are diffused into a gate electrode during the high temperature thermal treatment process, thereby degrades the performance properties of the semiconductor device.
In order to overcome this disadvantage, the flow process of the BPSG film must be performed at a temperature below 820xc2x0 C. In flow processes at temperatures below 820xc2x0 C., however, planarization of the BPSG film is generally not satisfactory.
Accordingly, an interconnection line formed on the interlayer insulating film having a poor planarization property is moved thereon during a succeeding thermal treatment process, and thus short may occur between the interconnection line and an adjacent metal electrode.
Even if the flow process is performed over 820xc2x0 C. on the BPSG film to improve the planarization property, subsequent movement of the interconnection line is not completely avoided, which degrades the performance of the semiconductor device.
In this regard, a conventional method for fabricating a semiconductor device will now be described with reference to FIGS. 1 to 4.
FIG. 1 is a cross-sectional view illustrating the conventional method for fabricating the semiconductor device.
FIG. 2 is a cross-sectional view illustrating the conventional method for fabricating the semiconductor device in a state where short is generated between a polysilicon electrode and a metal electrode due to a movement resulting from the thermal treatment process.
FIGS. 3 through 6 are graphs respectively showing the relation between the movement range of the polysilicon electrode due to the thermal processes as a function of variations in the design rules, the steps of the thermal treatment process, the thermal treatment process temperature and the ratio of boron and phosphorus in the BPSG film are varied.
As illustrated in FIG. 1, an active region and a device isolating region are defined by forming a device isolating film 2 on a semiconductor substrate 1.
A gate oxide film 3, a gate conductive film 4 and a hard mask film 5 are sequentially stacked on the active region where the device isolating film 2 is not formed.
The gate oxide film 3, gate conductive film 4 and hard mask film 5 are selectively patterned according to a photolithography and developing processes. Thereafter, spacers 7 are formed at the side portions of the patterned films, thereby forming a gate electrode.
On the other hand, the gate conductive film 4 and the hard mask film 5 are stacked on the active region where the device isolating film 2 is formed, and patterned in a predetermined shape. The spacers 7 are formed at the side portions of the patterned films to form the gate electrode.
A lightly-doped region 6a and a highly-doped region 6b are formed on the semiconductor substrate 1 of the active region, and thus a source region and a drain region are respectively defined.
A first interlayer insulating film having a stacked structure comprising a tetraethylorthosilicate (TEOS) oxide film 8 and a BPSG film 9 is formed on the gate electrode consisting of the gate oxide film 3, gate conductive film 4, hard mask film 5 and spacers 7. A polysilicon electrode 10 is formed above to serve as an interconnection line (the gate electrode).
Then, a second interlayer insulating film 11 is formed on the first interlayer insulating film to cover the polysilicon electrode 10.
A contact hole (not shown) is formed on the second interlayer insulating film 11. A metal electrode 12 is formed on the second interlayer insulating film 11 and extending through the contact hole to contact the source/drain region 6b of the active region.
Here, the interconnection line may comprise WSix, PtSix, CoSix, TiSix, and/or WSix/polysilicon.
In addition, the high temperature flow process is performed on the first interlayer insulating film to 8, 9 improve the planarization property.
As described above, when the stacked structure comprising the TEOS oxide film 8 and the BPSG film 9 is employed as the first interlayer insulating film, the polysilicon electrode 10 moves along the BPSG film 9 during the succeeding thermal treatment process, as shown in FIG. 2 (solid line), and may generate a short with the metal electrode 12.
Especially in those cases in which the thermal treatment process is performed below 820xc2x0 C., the resulting BPSG film 9 is not well planarized and, as a result, the polysilicon electrode 10 is often moved in adjacent regions having low pattern density.
FIG. 3 shows a movement range of the polysilicon electrode P2 when the design rules of the semiconductor devices range from 0.18 to 0.55 xcexcm and the thermal treatment process is performed at a temperature over 800xc2x0 C. at least three times.
Referring to FIG. 3, the polysilicon electrode P2 is moved on the BPSG film by at least 0.3 xcexcm as a result of the thermal treatment process.
In the case of a high integration semiconductor device having a design rule of 0.25 xcexcm, the interconnection line deposited on the BPSG film, such as the polysilicon electrode, is moved by more than 0.3 xcexcm due to the thermal treatment process, and thus increasing the likelihood of a short forming between the interconnection line and the metal electrode.
As illustrated in FIG. 4, when the flow process is carried out on the BPSG film at a temperature over 820xc2x0 C., the polysilicon electrode P2 is moved by 0.2 xcexcm as a result of a second thermal treatment process (second BPSG), and 0.35 xcexcm as a result of a third thermal treatment process (third BPSG).
As described above, the movement range of the polysilicon electrode P2 is increased by repetition of the thermal treatment process. Therefore, when a multi-step thermal treatment process is utilized, a short nearly always occurs between the polysilicon electrode P2 and the metal electrode.
As shown in FIG. 5, when the first thermal treatment process is performed at temperatures of 800xc2x0 C., 820xc2x0 C. and 850xc2x0 C., the polysilicon electrode P2 is moved by about 0.35 xcexcm, 0.31 xcexcm and 0.3 xcexcm, respectively.
Referring to FIG. 6, the movement range of the polysilicon electrode P2 on the BPSG film varies according to the content ratio of boron and phosphorus in the BPSG film being subjected to the high temperature flow process.
That is, when the flow process is performed at 850xc2x0 C., the movement range of the polysilicon layer is larger when a content ratio of boron to phosphorus is 4.5:4.2 (71) than when it is 4.0:4.2 (72).
However, in either case, the polysilicon electrode P2 is moved by more than 0.3 xcexcm.
As a result, when the thermal treatment process is performed below 820xc2x0 C. to prevent diffusion, and when the flow process is executed over 820xc2x0 C. to planarize the BPSG film, the polysilicon electrode P2 is moved by at least 0.3 xcexcm as a result of the multi-step thermal treatment process.
Degradation of the semiconductor device resulting from the movement of the polysilicon electrode is not monitored and/or confirmed by using a test pattern until the fabrication process is completely finished. Thus, it is a very serious and costly problem in the fabrication process of the semiconductor device.
FIGS. 7 and 8 are cross-sectional views illustrating a semiconductor device fabricated in accordance with the conventional method for overcoming such a disadvantage. That is, FIGS. 7 and 8 are cross-sectional views of a technique for preventing shorts from occurring between the polysilicon electrode and the metal electrode.
As illustrated in FIG. 7, the first interlayer insulating film having the stacked structure of the TEOS oxide film 8 and the BPSG film 9 is formed to cover the gate electrode formed on the active region and the device isolating film 2, as in FIG. 1.
Thereafter, oxynitride layer (SION) 20 for fixing the first insulating film having the stacked structure of the TEOS oxide film 8 and the BPSG film 9 is deposited. The polysilicon electrode P2 is formed thereon. The succeeding procedure is the same as the procedure in FIG. 1.
Here, the silicon oxynitride film 20 both prevents impurities from the first interlayer insulating film from diffusing into the polysilicon electrode 10, and enhances adherence of the polysilicon electrode 10, thereby reducing the movement thereof.
As depicted in FIG. 8, the first interlayer insulating film having the stacked structure of the TEOS oxide film 8 and the BPSG film 9 is formed to cover the gate electrode formed on the active region and the device isolating film 2, as in FIG. 7. A first silicon oxynitride film 20 is deposited, and the polysilicon electrode 10 is formed thereon.
A second oxynitride film 30 is formed on the first silicon oxynitride film 20 to cover the polysilicon electrode 10. The subsequent processing is similar to the procedure illustrated in FIG. 1.
As did the silicon oxynitride film in FIG. 7, the first silicon oxynitride film 20 prevents impurities from being diffused into the polysilicon electrode 10, and enhances adherence of the polysilicon electrode 10.
Furthermore, the second silicon oxynitride film 30 decreases the movement of the polysilicon electrode 10 by enhancing adherence to the first silicon oxynitride film 20, and prevents impurities from the second interlayer insulating film 11 from diffusing into the polysilicon electrode 10 during subsequent thermal treatment processes.
As discussed earlier, the conventional method for fabricating the semiconductor device has the following disadvantages:
When the silicon oxynitride film is formed at the upper or lower portion of the polysilicon electrode, the movement of the polysilicon electrode cannot be completely prevented during the succeeding thermal treatment process.
Accordingly, the movement range of the polysilicon electrode is gradually increased during the thermal treatment process. In the case of the semiconductor device having a design rule below 0.2 xcexcm, short is typically generated between the polysilicon electrode 10 and the metal electrode 12.
In addition, when the silicon oxynitride film is formed at the upper or lower portion of the polysilicon electrode and the thermal treatment process is performed at a temperature over 820xc2x0 C., the polysilicon electrode is moved by the flow of the interlayer insulating film comprising the BPSG film. To prevent this movement, therefore, the thermal treatment process must be performed below 820xc2x0 C.
A method for preventing a short between the polysilicon electrode and the metal electrode by forming a spacer in the contact hole has been suggested. This method relies on the spacer to insulate the metal electrode even if the polysilicon electrode is moved due to a subsequent thermal treatment process.
However, this method requires at least 10 additional steps to form the spacer in the contact hole, and further requires that a plug ion implantation process be selectively performed in the P+ regions and the N+ regions.
Accordingly, a primary object of the present invention is to provide a method for fabricating a semiconductor device which can prevent shorts from occurring between an interconnection line and a metal electrode.
Another object of the present invention is to provide a method for fabricating a semiconductor device which can improve electrical properties of the semiconductor device by eliminating leakage currents due to shorts between an interconnection line and a metal electrode.
Still another object of the present invention is to provide a method for fabricating a semiconductor device which can reduce fabrication costs and increase efficiency, by limiting or eliminating movement of an interconnection line only by adding only a one-step process.
Still another object of the present invention is to provide a method for fabricating a semiconductor device which can increase the yield of the semiconductor device and allow a uniform and stabilized fabrication process.
In order to achieve the above-described objects of the present invention, a method for fabricating a semiconductor device is provided that includes the steps of: forming a transistor on a semiconductor substrate; forming a first interlayer insulating film over the entire structure, including the transistor; planarizing the first interlayer insulating film; forming a stabilized insulating film consisting of an insulating material of low thermal expansion and shrinkage on the first interlayer insulating film; forming an interconnection line on the stabilized insulating film; forming a second interlayer insulating film on the stabilized insulating film in order to cover the interconnection line; and forming a metal electrode on the second interlayer insulating film in order to contact the semiconductor substrate.
A method for fabricating a semiconductor device is also provided that includes the steps of: forming a transistor on a semiconductor substrate; forming a first interlayer insulating film having a stacked structure of TEOS/BPSG films over the entire structure including the transistor; planarizing the first interlayer insulating film in accordance with flow and etching processes; forming a stabilized insulating film consisting of an insulating material of low thermal expansion and shrinkage on the first interlayer insulating film; forming an interconnection line on the stabilized insulating film; forming a second interlayer insulating film on the stabilized insulating film in order to cover the interconnection line; and forming a metal electrode on the second interlayer insulating film in order to contact the semiconductor substrate.